The present invention relates to computer apparatus. More particularly, it relates to apparatus for controlling the operation of a computer memory.
One form of memory unit for a computer is a volatile memory wherein the memory cells must be periodically refreshed in order to maintain the information stored in that memory. There have been many circuits provided for controlling the refreshment of such memory cells. One such refresh control circuit is shown in a copending application of Richard C. Moffett, Ser. No. 387,732. In that case, apparatus is provided for the periodic refreshing of memory cells in groups while providing logic elements for avoiding access conflicts between the refresh operation and data transactions in the memory.
Another feature of computer operations is that both the software and the hardware must be debugged. An effective way of debugging in the system is to put the operation into a so-called step mode where a transaction is accomplished one step at a time. The result of each step may then be checked to determine where an error has occured, that it may be corrected. Such a step mode is, or may be, accomplished by inhibiting a normal free running clock and issuing controlling clock pulses on a step by step basis.
In a static memory, such a step mode presents no problem. In a voltile memory, such as a MOS memory, however, the step mode must be reconciled with a need for a periodic refreshment of the memory cells. The memory timing must be uninterrupted to protect the memory devices. So far as is here known, the problem has not been previously addressed.